KeeloqGrabber — Part 2. Quartus Project

In the second part of the article, we will prepare the Quartus development environment and create a new KeeloqGrabber project. All examples were created using Quartus 13.1, but the steps are almost identical in newer versions.

1. Create a new project
Start Quartus and create a new project by selecting:
File → New Project Wizard

2. Set the working directory
Specify the working directory and the project name keeloq_grab, then click Next.

3. Add existing files
The wizard will ask if you want to add existing files to the project. In our case, we do not have any files yet, so simply click Next.

4. Select the FPGA device
Now we need to select the FPGA device we will be working with. Since the device list is quite large, we will use the following filters:


Family: Cyclone V
Devices: Cyclone V SE Mainstream
SpeedGrade: 6
From the list that appears, select: 5CSEMA5F31C6
Then click Next.

5.  Skip the EDA Tools tab by clicking Next.

6. Project Summary
The Summary page will appear. Verify that all settings are correct and click Next.

7. Create a SystemVerilog source file
We now have an empty project. Let's add a SystemVerilog source file.
Select:
File → New → SystemVerilog HDL File

8. Create the module interface
In the opened SystemVerilog file, write the module interface:

module keeloq_grab(
ref_clk_i,
signal_i,
uart_tx_o
);

(* chip_pin = "AF14" *) input ref_clk_i; // 50 MHz
(* chip_pin = "Y17" *) input signal_i; // data signal from 433.92 receiver
(* chip_pin = "AC18" *) output uart_tx_o;

endmodule


Our project uses three external FPGA pins:
ref_clk_i - external 50 MHz clock source taken from the DE1 development board.
signal_i - GPIO pin on the development board connected to the 433.92 MHz receiver output.
uart_tx_o - GPIO pin connected to the RX input of a UART-USB converter.

Save the file as: keeloq_grab.sv
Save it in the project working directory.

9. Compile the project
Start project compilation by pressing:
Ctrl + L

10. Configure I/O standards
Although we defined the FPGA pins directly in the keeloq_grab.sv file, we still need to configure the I/O Standard for each pin.
Open:
Assignments → Pin Planner
Set the I/O Standard as shown in the figure.

If the assigned pins do not appear in the Pin Planner, run compilation again using:
Ctrl + L

Conclusion
At this point, the project setup is complete.
In the next article we will configure IP cores: FIFO, PLL
Create a constraints file for the TimeQuest Analyzer