Building a KeeLoq Grabber on FPGA — Part 1: Overview

This is the introductory part of a series of articles dedicated to FPGA development. Our goal will be to create a grabber for KeeLoq packets transmitted at a frequency of 433.92 MHz.
The KeeLoq cipher, originally created in the mid-1980s for car alarm systems, has since become widely used in many other applications. Radio key fobs based on HCS301 or HCS360 microchips are used to control barriers, automatic gates, and other security systems.
In this article we will analyze how to capture transmissions from a radio key fob based on the HCS301 chip.
It should be noted that simply receiving radio packets from the air does not violate the law. All examples in this article are provided for demonstration purposes only.

Hardware Used in the Project
The following hardware modules will be used in this series of articles.

1. FPGA Development Board — Altera Cyclone V DE1-SoC

It should be noted that almost any FPGA board based on Altera devices can be used as a development platform. The only requirement is that the board provides GPIO pins.

2. RF Receiver Module — RR10 (433.92 MHz)

3. UART–USB Converter Based on FT232RL

4. Radio Key Fob Based on the HCS301 Chip

Connection Diagram

Only two GPIO pins of the FPGA are required.
Connections:
DE1 connector JP1 pin 0 — FT232 UART RX
DE1 connector JP1 pin 1 — RR10 DATA
After powering the system, the RR10 receiver starts outputting data (including noise) to pin 1 of the development board.
The task of the FPGA is to:
1. filter out the noise,
2. detect and extract the KeeLoq packet,
3. transmit the received data to a computer via UART.

Debugging the System
To better understand the behavior of each module, it is useful to have an oscilloscope available.
However, in this series I will try to describe the entire development process using only the standard FPGA debugging tools.

Software Requirements
For development we will use:
Quartus 13.1 or newer

In the next article we will examine:
• creating a project in Quartus
• assigning FPGA pins
• creating timing constraints for the KeeLoq grabber project.